A sampling circuit, such as an analog to digital converter (ADC), converts a continuous time signal into a discrete time signal formed of a sequence of discrete signal samples. In the case of an ADC, each discrete signal sample is further digitized into a binary string representative of the discrete signal sample value to form a digital output signal. The sampling circuit commonly uses a capacitor (or other charge storage device) to sample the continuous time input signal value at a given instant in time. The sampling circuit passes the sampled signal value to a conversion circuit, or otherwise makes use of the sampled signal value stored on the capacitor.
The sampling circuit operates at a determined sampling rate fs to take one sample of the continuous time input signal every 1/fs seconds. The sample rate is application dependent and specifies the frequency at which the input signal is sampled for conversion to a digital word. In order to sample a continuous-time signal and avoid aliasing, the sampling rate fs must be at least twice the highest frequency of the continuous-time signal. If the sampling rate fs is not twice the highest frequency of the continuous-time signal, aliasing or folding of high-frequency components of the input signal into the post-sampling bandwidth occurs according to Nyquist's sampling theorem. These folding effects introduce noise and error into the sampled signal, and must be addressed to prevent undesired signals and undesired noise from appearing in-band.
FIG. 1 illustrates an ADC 103 sampling an input signal Vin. Vin is converted as expected between a frequency of 0 and fs/2. However above fs/2 in region A, the input signal, which may be a random (noise) or a deterministic signal, is folded between fs/2 and 0. Thus, an input signal component with a frequency of fs gets folded back and appears as a DC signal. As the frequency increases into region B (beyond region A), the input signal energy gets folded back and forth across the output bandwidth of 0 to fs/2.
FIG. 2 illustrates a method of reducing the effects of aliasing. A low pass filter 201 takes the input signal 200 and filters out or attenuates the frequency components that will be aliased according to transition and stopband attenuation 206, presenting this band-limited signal to an input 202 of the ADC 203. Because the input signal has reduced energy in region 210, the amount of energy that will be folded into the digital output is reduced, thereby providing for lower aliasing noise and improved performance. However, it is difficult to provide a filter with a sharp cutoff before the ADC 203. If an active filter is used for faster transition between pass-band and stop-band, additional noise is introduced by the active filter, additional current is required by the active filter, and the output of the active filter must be able to drive the input of the ADC 203.
FIG. 3 illustrates another method for addressing the effects of aliasing of an input signal. In FIG. 3, input signal 300 is sampled by ADC 301 at a rate fshf substantially higher than the bandwidth of interest 309 (fshf>>fs). Any signals above the bandwidth of interest but within bandwidth 308 are accurately sampled by the ADC and presented as a digital signal to output 302. The digital output 302 is filtered by a digital filter 303 (having a filter characteristic 310) and presented to output 304. In one example, filter 303 is a decimation filter with down-sampling. According to this method, aliasing is avoided by increasing the ADC sample rate over the rate required to convert signals in the bandwidth of interest. The out-of-band signals are then removed using the digital filter 303. An analog anti-aliasing filter having a low-pass characteristic 306 may be used in front of the ADC 301 to further prevent aliasing. By separating the bandwidth of interest farther from the point where aliasing starts to occur the design of an analog anti-aliasing filter may be greatly simplified, and the signal processing for filtering out of band signals may be performed in the digital domain, where sharper, more stable filter characteristics can be realized. However, in conjunction with increased computational power, the need for a faster ADC to oversample the input signal wastes substantial power.
A need therefore exists for energy-efficient circuits and methods for sampling of continuous time signals that have low sensitivity to noise, low sensitivity to aliasing, operate with low power consumption, and are capable of operating at high sampling rates.